1. Field of the Invention
This invention is related to the field of integrated circuits, and more particularly, to methods and systems for measuring and adjusting various characteristic of clock signals, such as clock skew, duty cycle and jitter.
2. Description of the Related Art
Typically, complex logic core designs rely on one or more clocks for operational synchronization. Some of the desirable qualities for a clock signal may be an extremely small period, very short rise and/or fall times, low jitter, available everywhere on the chip with very low skew, and the ability to drive heavy loads at any point on the chip, while consuming the least possible amount of power.
Clock skew may be defined as the difference in time between simultaneous clock transitions within a system. Skew has become the major part of constraints that form the upper boundary for the system clock frequency. Clock skew refers to a phenomenon in which a clock signal arrives at different components at different times. The difference in arrival time may be caused by the clock signal traveling different distances to different components or may also be caused by defect or flow in materials or manufacturing causing the clock signal to travel faster or slower along a pathway than expected.
Reduction in system clock skew may also reduce costs by avoiding complicated architecture or faster logic. To ensure that a clocking network operates as closely to the ideal as possible, skew may be minimized along the entire clocking network. This ensures that all sequential elements see a common clock edge. Buffer delays and wiring delays are the two most significant factors contributing to skew. The clock topology can significantly contribute to skew.
Jitter can be defined as the deviations in a clock's output transition from their ideal positions. The deviation can either be leading or lagging behind the ideal position. Jitter is usually specified in +/− picoseconds. Jitter measurements can be classified into three categories: cycle-to-cycle jitter, period jitter, and long-term jitter. Cycle-to-cycle jitter is the change in a clock's output transition from its corresponding position in the previous cycle. Period jitter is the maximum change in a clock's output transition from its ideal position. Long-term jitter measures the maximum change in a clock's output transition from its ideal over a large number of cycles.